1. Field of the Invention
The present invention is related to a shift register, and more particularly, to a shift register capable of reducing coupling effect.
2. Description of the Prior Art
Liquid crystal display (LCD) devices, characterized in low radiation, small size and low power consumption, have gradually replaced traditional cathode ray tube (CRT) display devices and been widely used in electronic devices, such as notebook computers, personal digital assistants (PDAs) or mobile phones. Traditional LCD devices display images by driving the pixels of the panel using external driving chips. In order to reduce the number of devices and to lower manufacturing cost, gate on array (GOA) technique has been developed in which the driving circuits are directly fabricated on the panel.
Reference is made to FIG. 1 for a simplified block diagram illustrating a prior art LCD device 100. FIG. 1 only shows partial structure of the LCD device 100, including a plurality of gate lines GL(1)-GL(N), a shift register 110, a clock generator 120 and a power supply 130. The clock generator 120 can provide a start pulse signal VST and two clock signals CLK1 and CLK2 for operating the shift register 110. The power supply 130 can provide bias voltages VDD and VSS for operating the shift register 110. The shift register 110 includes a plurality of shift register units SR(1)-SR(N) coupled in series and having output ends respectively coupled to the corresponding gate lines GL(1)-GL(N). According to the clock signals CLK1, CLK2 and the start pulse signal VST, the shift register 110 can sequentially output gate driving signals GS(1)-GS(N) to the corresponding gate lines GL(1)-GL(N) via the shift register units SR(1)-SR(N), respectively.
Reference is made to FIG. 2 for a diagram illustrating an nth-stage shift register unit SR(n) among the prior art shift register units SR(1)-SR(N), wherein n is an integer between 1 and N. The nth-stage shift register unit SR(n) includes an input end IN(n), an output end OUT(n), an input circuit 10, a pull-up circuit 20, two pull-down circuits 30 and 34, and a holding circuit 40. The input end IN(n) of the shift register unit SR(n) is coupled to the output end OUT(n−1) of a prior-stage shift register unit SR(n−1), and the output end OUT(n) of the shift register unit SR(n) is coupled to the input end IN(n+1) of a next-stage shift register unit SR(n+1).
The input circuit 10 includes a transistor switch T1 having a gate and a drain coupled to the input end IN(n) and a source coupled to a node Q(n). The input circuit 10 can thus control the signal transmission path between the input end IN(n) and the node Q(n) according to the gate driving signal GS(n−1). The pull-up circuit 20 includes a transistor switch T2 having a gate coupled to the node Q(n), a drain coupled to the clock generator 120 for receiving the clock signal CLK1, and a source coupled to the output end OUT(n). The pull-up circuit 20 can thus control the signal transmission path between the clock signal CLK1 and the output end OUT(n) according to the voltage level of the node Q(n).
The pull-down circuit 30 includes transistor switches T3-T6. The transistor switches T3 and T4 coupled in series respectively receive the clock signals CLK1 and CLK2 having opposite phases at corresponding gates, and can thus provide control signals at the gates of the transistor switches T5 and T6 accordingly. Therefore, the transistor switch T5 can control the signal transmission path between the node Q(n) and the bias voltage VSS according to its gate voltage, while the transistor switch T6 can control the signal transmission path between the output end OUT (n) and the bias voltage VSS according to its gate voltage. The pull-down circuit 34 includes transistor switches T7-T10. The transistor switches T7 and T8 coupled in series respectively receive the clock signals CLK1 and CLK2 having opposite at the gates of the transistor switches T9 and T10 accordingly. Therefore, the transistor switch T9 can control the signal transmission path between the node Q(n) and the bias voltage VSS according to its gate voltage, while the transistor switch T10 can control the signal transmission path between the output end OUT(n) and the bias voltage VSS according to its gate voltage.
The holding circuit 40 includes transistor switches T11-T13. The transistor switch T11 having a gate coupled to the output end OUT(n) can maintain the gates of the transistor switches T5 and T6 at the low level bias voltage VSS when the gate driving signal GS(n) is at high level. The transistor switch T12 having a gate coupled to the input end IN(n) can maintain the gates of the transistor switches T9 and T10 at the low level bias voltage VSS when the gate driving signal GS(n−1) is at high level. The transistor switch T13 having a gate coupled to the output end OUT(n) can maintain the gates of the transistor switches T9 and T10 at the low level bias voltage VSS when the gate driving signal GS(n) is at high level.
Reference is made to FIG. 3 for a timing diagram illustrating the operation of the prior art LCD device 100. In the prior art LCD device 100, the duty cycles of the clock signals CLK1 and CLK2 are both ½ and the clock signals CLK1 and CLK2 have opposite phases. The first-stage shift register unit SR(1) generates the first-stage gate driving signal GS(1) according to the start pulse signal VST, and the second- to Nth-stage shift register units SR(2)-SR(N) generate the second- to Nth-stage gate driving signals GS(2)-GS(N) according to the output signals of the corresponding prior-stage shift registers (FIG. 3 only shows the gate driving signals GS(1), GS(n−1) and GS(n)). In other words, the gate driving signals GS(1)-GS(N−1) are provided for enabling the shift register units SR(2)-SR(N), respectively.
The prior art LCD device 100 performs pull-up operations between t1 and t3, and performs pull-down operations after t3. Between t1 and t2, the clock signal CLK1 is at low level, while the clock signal CLK2 and the gate driving signal GS(n−1) are at high level. The transistor switch T1 is thus turned on and the node Q(n) is pulled up to a high level VDD, thereby turning on the transistor switch T2. At t2, the clock signal CLK1 switches from low level to high level, thereby turning on the transistor switch T2 for providing the gate driving signal GS(n) with high level between t2 and t3 (when the clock signal CLK1 is at high level). On the other hand, the pull-down circuits 30 and 40 operate in a complementary manner and each performs 50% of the pull-down operations. Between t3 and t4, the clock signal CLK1 is at low level, the clock signal CLK2 is at high level, and the input and output signals of the shift register unit SR(N) (the gate driving signals GS(n−1) and GS(n)) are both at low level. The gates of the transistor switches T5 and T6 are substantially maintained at a low level VSS, and the gates of the transistor switches T9 and T10 are substantially maintained at the high level VDD. Similarly, between t4 and t5, the clock signal CLK1 is at high level, the clock signal CLK2 is at low level, and the output signal of the shift register unit SR (N) (the gate driving signal GS (n)) is at low level. The gates of the transistor switches T5 and T6 are substantially maintained at the high level VDD, and the gates of the transistor switches T9 and T10 are substantially maintained at the low level VSS. For the nth-stage shift register unit SR(n), the voltage level of the node Q(n) needs to change between t1 and t2, but is required to stably remain at low level during other periods. In the ideal case, the transistor switch T2 can be completely turned off, so that the clock signal CLK1 does not influence the voltage level of the node Q(n). However in the actual situation, the clock signal CLK1 may be coupled to the node Q(n) via the parasite capacitance of the transistor switch T2. The performance of the LCD device 100 is influenced since the voltage level of the node Q(n) may fluctuate with the clock signal CLK1, such as at t4, t4 and t6.